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| a FEATURES Fully Buffered Inputs and Outputs Fast Channel-to-Channel Switching: 15 ns High Speed 380 MHz Bandwidth (-3 dB) 200 mV p-p 310 MHz Bandwidth (-3 dB) 2 V p-p 1000 V/ s Slew Rate G = +1, 2 V Step 1150 V/ s Slew Rate G = +2, 2 V Step Fast Settling Time of 15 ns to 0.1% Low Power: 25 mA Excellent Video Specifications (RL = 150 ) Gain Flatness of 0.1 dB to 90 MHz 0.01% Differential Gain Error 0.02 Differential Phase Error Low All-Hostile Crosstalk -84 dB @ 5 MHz -54 dB @ 50 MHz Low Channel-to-Channel Crosstalk -56 dB @ 100 MHz High "OFF" Isolation of -100 dB @ 10 MHz Low Cost Fast High Impedance Output Disable Feature for Connecting Multiple Devices APPLICATIONS Pixel Switching for "Picture-In-Picture" Switching RGB in LCD and Plasma Displays RGB Video Switchers and Routers IN0A 1 DGND 2 IN1A 3 GND 4 IN2A 5 VCC 6 VEE 7 IN2B 8 GND 9 IN1B 10 GND 11 IN0B 12 380 MHz, 25 mA, Triple 2:1 Multiplexers AD8183/AD8185* FUNCTIONAL BLOCK DIAGRAM AD8183/AD8185 SELECT 24 VCC 23 OE 22 SEL A/B DISABLE 0 21 VCC 20 OUT0 19 VEE 1 18 OUT1 17 VCC 2 16 OUT2 15 VEE 14 DVCC 13 VCC Table I. Truth Table SEL A/B 0 1 0 1 OE 0 0 1 1 OUT INA INB High Z High Z PRODUCT DESCRIPTION The AD8183 (G = +1) and AD8185 (G = +2) are high speed triple 2:1 multiplexers. They offer -3 dB signal bandwidth up to 380 MHz, along with slew rate of 1000 V/s. With better than -90 dB of channel-to-channel crosstalk and isolation at 10 MHz, they are useful in many high-speed applications. The differential gain and differential phase errors of 0.01% and 0.02 respectively, along with 0.1 dB flatness to 90 MHz make the AD8183 and AD8185 ideal for professional video and RGB multiplexing. They offer 15 ns channel-to-channel switching time, making them an excellent choice for switching video signals, while consuming less than 25 mA on 5 V supply voltages. Both devices offer a high speed disable feature that can set the output into a high impedance state. This allows the building of larger input arrays while minimizing "OFF" channel output loading. They operate on voltage supplies of 5 V and are offered in a 24-lead TSSOP package. VO = 1.4V STEP 1.4V RL = 150 1.2V 1.0V 0.8V 0.6V 0.4V 0.2V 0.0V 200mV 2ns Figure 1. AD8185 Pulse Response; RL = 150 *Patents pending. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999 AD8183/AD8185-SPECIFICATIONS(T = 25 C, V = A S 5 V, RL = 1 k Min 250/300 200/250 250/300 200/250 unless otherwise noted) Typ 590/360 380/320 530/350 310/300 90/60 100/160 1000/1150 15 0.01 0.02 -84/-72 -54/-50 -56/-54 -100 28/15 0.20 5 10 1 15 6/10 0.25/0.85 25/40 25/40 10/15 Max Unit MHz MHz MHz MHz MHz MHz V/s ns % Degrees dB dB dB dB nV/Hz % mV mV mV V/C A M pF pF V V V mA M pF 5.5 66/72 56/68 25 3/7 25 V dB dB mA mA mA Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth (Small Signal) -3 dB Bandwidth (Small Signal) -3 dB Bandwidth (Large Signal) -3 dB Bandwidth (Large Si 0.1 dB Bandwidth Slew Rate Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Differential Gain Differential Phase All-Hostile Crosstalk, RTI Channel-to-Channel Crosstalk, RTI OFF Isolation Voltage Noise, RTI DC PERFORMANCE Voltage Gain Error Input Offset Voltage, RTI Input Offset Voltage Matching, RTI Input Offset Drift, RTI Input Bias Current INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Voltage Range OUTPUT CHARACTERISTICS Output Voltage Swing Short Circuit Current Output Resistance Output Capacitance POWER SUPPLY Operating Range Power Supply Rejection Ratio Power Supply Rejection Ratio Quiescent Current Condition VOUT = 200 mV p-p VOUT = 200 mV p-p, R L = 150 VOUT = 2 V p-p VOUT = 2 V p-p, RL = 150 VOUT = 200 mV p-p VOUT = 200 mV p-p, R L = 150 2 V Step 2 V Step, RL = 150 NTSC or PAL, 150 NTSC or PAL, 150 = 5 MHz, AD8185: R L = 150 = 50 MHz, AD8185: RL = 150 = 100 MHz, AD8185: R L = 150 = 10 MHz, RL = 150 = 10 kHz to 30 MHz No Load TMIN to TMAX Channel-to-Channel 4/1 Channel Enabled Channel Disabled 8/5 1 1.5 3.0/ 1.5 3.25 2.95 60 0.3 8/3 4/6.5 RL = 1 k RL = 150 Enabled Disabled Disabled 2.90 2.65 4/1 +PSRR +V S = +4.5 V to +5.5 V, -V S = -5 V -PSRR -VS = -4.5 V to -5.5 V, +VS = +5 V All Channels "ON" All Channels "OFF" TMIN to TMAX ; All Channels "ON" Channel-to-Channel IN0 = +1 V, IN1 = -1 V INPUT = 1 V INPUT = 1 V All Inputs Grounded SEL A/B and OE Inputs SEL A/B and OE Inputs SEL A/B and OE = 4 V SEL A/B and OE = 0.4 V Operating (Still Air) Operating (Still Air) Operating 4.5 58/62 52/60 30 5/10 SWITCHING CHARACTERISTICS Switch Time 50% Logic to 50% Output Settling ENABLE to Channel ON Time 50% Logic to 50% Output Settling ENABLE to Channel OFF Time 50% Logic to 50% Output Settling Channel Switching Transient (Glitch) DIGITAL INPUTS Logic "1" Voltage Logic "0" Voltage Logic "1" Input Current Logic "0" Input Current OPERATING TEMPERATURE RANGE Temperature Range JA JC Specifications subject to change without notice. 15 20 45 50/70 2.0 0.8 10 0.5 -40 128 42 +85 ns ns ns mV V V nA A C C/W C/W -2- REV. 0 AD8183/AD8185 MAXIMUM POWER DISSIPATION - Watts ABSOLUTE MAXIMUM RATINGS 1 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.0 V DVCC to VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.2 V Internal Power Dissipation2, 3 AD8183/AD8185 24-Lead TSSOP (RU) . . . . . . . . . . . . . 1 W Input Voltage IN0A, IN0B, IN1A, IN1B, IN2A, IN2B . . . . . VEE VIN V CC SELECT A/B, OE . . . . . . . . . . . . . . . . . . DGND VIN VCC Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . Indefinite3 Storage Temperature Range . . . . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering 10 sec) . . . . . . . . . . . 300C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air (T A = 25C). 3 24-lead plastic TSSOP; JA = 128C/W. Maximum internal power dissipation (P D) should be derated for ambient temperature (T A) such that PD < (150C-T A)/JA. 2.0 TJ = 150 C 1.5 1.0 0.5 0 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 AMBIENT TEMPERATURE - C 80 90 Figure 2. Maximum Power Dissipation vs. Temperature PIN CONFIGURATION IN0A 1 DGND 2 IN1A 3 GND 4 IN2A 5 VCC 6 24 23 22 21 ORDERING GUIDE Model AD8183ARU AD8185ARU AD8183-EVAL AD8185-EVAL Temperature Range -40C to +85C -40C to +85C Package Description 24-Lead Plastic TSSOP 24-Lead Plastic TSSOP Evaluation Board Evaluation Board Package Option RU-24 RU-24 VCC OE SEL A/B VCC OUT0 AD8183/ AD8185 20 19 VEE TOP VIEW VEE 7 (Not to Scale) 18 OUT1 17 16 15 14 13 MAXIMUM POWER DISSIPATION IN2B 8 GND 9 IN1B 10 GND 11 IN0B 12 VCC OUT2 VEE DVCC VCC The maximum power that can be safely dissipated by the AD8183/ AD8185 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175C for an extended period can result in device failure. While the AD8183/AD8185 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (150C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves shown in Figure 2. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8183/AD8185 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. 0 -3- AD8183/AD8185 1 0 -1 -2 FLATNESS GAIN - dB -3 -4 -5 -6 -7 -8 -9 0.1 1 10 FREQUENCY - MHz 100 1k VO AS SHOWN RL = 150 200mV p-p 2V p-p 2V p-p 0.1 0 FLATNESS - dB -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 NORMALIZED GAIN - dB GAIN 200mV p-p 1 GAIN 0 -1 2V p-p -2 FLATNESS -3 -4 -5 -6 -7 -8 -9 0.1 1 10 FREQUENCY - MHz 100 VO AS SHOWN RL = 150 200mV p-p 2V p-p 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 1k NORMALIZED FLATNESS - dB NORMALIZED FLATNESS - dB 200mV p-p Figure 3. AD8183 Frequency Response; RL = 150 Figure 6. AD8185 Frequency Response; RL = 150 1 0 -1 -2 FLATNESS GAIN - dB -3 -4 -5 -6 -7 -8 -9 0.1 1 10 FREQUENCY - MHz 100 VO AS SHOWN RL = 1k 2V p-p GAIN 2V p-p 200mV p-p 0.3 0.2 0.1 FLATNESS - dB 0 -0.1 -0.2 -0.3 200mV p-p -0.4 -0.5 -0.6 1k NORMALIZED GAIN - dB 2 1 GAIN 0 200mV p-p 0.3 0.2 2V p-p 0.1 0 200mV p-p 2V p-p VO AS SHOWN RL = 1k -0.1 -0.2 -0.3 -0.4 -0.5 1 10 FREQUENCY - MHz 100 -0.6 1k -1 FLATNESS -2 -3 -4 -5 -6 -7 -8 0.1 Figure 4. AD8183 Frequency Response; RL = 1 k Figure 7. AD8185 Frequency Response; RL = 1 k 5 4 3 2 GAIN - dB 1 0 -1 -2 -3 -4 -5 0.1 1 10 FREQUENCY - MHz 100 1k -40 C VO = 200mV p-p RL = 1k CL = 5pF TEMPERATURE AS SHOWN +25 C +85 C 4 3 2 NORMALIZED GAIN - dB 1 0 -1 -2 -3 -4 -5 -6 0.1 1 10 FREQUENCY - MHz 100 1k -40 C VO = 200mV p-p RL = 150 CL = 5pF TEMPERATURE AS SHOWN +25 C +85 C Figure 5. AD8183 Frequency Response vs. Temperature Figure 8. AD8185 Frequency Response vs. Temperature -4- REV. 0 AD8183/AD8185 -10 -20 -30 CROSSTALK - dB CROSSTALK - dB -40 -50 ALL-HOSTILE -60 ADJACENT -70 -80 -90 -100 -110 1 10 100 FREQUENCY - MHz 1k RL = 1k RT = 37.5 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 1 10 100 FREQUENCY - MHz 1k ADJACENT ALL-HOSTILE RL = 150 RT = 37.5 RTI MEASURED Figure 9. AD8183 Crosstalk vs. Frequency Figure 12. AD8185 Crosstalk vs. Frequency -10 CHANNEL-TO-CHANNEL CROSSTALK - dB CHANNEL-TO-CHANNELCROSSTALK - dB -20 -30 -40 -50 -60 DRIVE B, LISTEN A -70 -80 DRIVE A, LISTEN B -90 -100 -110 1 10 100 FREQUENCY - MHz 1k RL = 1k RT = 37.5 -10 -20 -30 -40 -50 -60 -70 -80 DRIVE B, LISTEN A -90 -100 -110 1 10 100 FREQUENCY - MHz 1k DRIVE A, LISTEN B RL = 150 RT = 37.5 RTI MEASURED Figure 10. AD8183 Channel-to-Channel Crosstalk vs. Frequency Figure 13. AD8185 Channel-to-Channel Crosstalk vs. Frequency 0 -10 -20 DISTORTION - dBc DISTORTION - dBc -30 -40 -50 SECOND HARMONIC -60 -70 THIRD HARMONIC -80 -90 -100 1 10 FUNDAMENTAL FREQUENCY - MHz 100 VO = 2V p-p RL = 150 0 -10 -20 -30 -40 -50 SECOND HARMONIC -60 -70 THIRD HARMONIC -80 -90 -100 1 10 FUNDAMENTAL FREQUENCY - MHz 100 VO = 2V p-p RL = 150 Figure 11. AD8183 Distortion vs. Frequency Figure 14. AD8185 Distortion vs. Frequency REV. 0 -5- AD8183/AD8185 0 1M 1M 1M INPUT IMPEDANCE - INPUT IMPEDANCE - 100k 100k 10k 10k 1k 1k 100 0.1 1 10 FREQUENCY - MHz 100 1k 100 0.1 1 10 FREQUENCY - MHz 100 1k Figure 15. AD8183 Input Impedance vs. Frequency Figure 18. AD8185 Input Impedance vs. Frequency 1k 1k 1k 100 OUTPUT IMPEDANCE - OUTPUT IMPEDANCE - 100 10 10 1 1 0.1 0.1 1 10 FREQUENCY - MHz 100 1k 0.1 0.1 1 10 FREQUENCY - MHz 100 1k Figure 16. AD8183 Output Impedance vs. Frequency; Enabled Figure 19. AD8185 Output Impedance vs. Frequency; Enabled 1M 1M 100k OUTPUT IMPEDANCE - OUTPUT IMPEDANCE - 1 10 FREQUENCY - MHz 100 1k 100k 10k 10k 1k 1k 100 100 10 0.1 10 0.1 1 10 FREQUENCY - MHz 100 1k Figure 17. AD8183 Output Impedance, vs. Frequency; Disabled Figure 20. AD8185 Output Impedance vs. Frequency; Disabled -6- REV. 0 AD8183/AD8185 -40 -50 -60 OFF ISOLATION - dB OFF ISOLATION - dB 1 10 FREQUENCY - MHz 100 500 -70 -80 -90 -100 -110 -120 -130 -140 0.1 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.1 1 10 FREQUENCY - MHz 100 500 Figure 21. AD8183 Off Isolation, Input-Output Figure 24. AD8185 Off Isolation, Input-Output -10 0 10 20 PSRR - dB PSRR - dB 30 -PSRR 40 50 +PSRR 60 70 80 0.1 1 10 FREQUENCY - MHz 100 -10 0 10 20 30 40 50 60 70 80 0.1 1 10 FREQUENCY - MHz 100 -PSRR +PSRR Figure 22. AD8183 PSRR vs. Frequency Figure 25. AD8185 PSRR vs. Frequency 170 150 VOLTAGE NOISE - nV/ Hz 130 110 90 70 50 30 10 VOLTAGE NOISE - nV/ Hz 170 150 130 110 90 70 50 30 10 10 100 1k 10k 100k FREQUENCY - Hz 1M 10M 10 100 1k 10k 100k FREQUENCY - Hz 1M 10M Figure 23. AD8183 Voltage Noise vs. Frequency Figure 26. AD8185 RTI Voltage Noise vs. Frequency REV. 0 -7- AD8183/AD8185 VO = 2V STEP RL = 150 VO = 2V STEP RL = 150 0.1%/DIV 0.1%/DIV 0 0 5 10 15 20 25 30 5ns/DIV 35 40 5 10 15 20 25 30 5ns/DIV 35 40 Figure 27. AD8183 0.1% Settling Time Figure 30. AD8185 0.1% Settling Time 100 90 +1.8V SEL A/B +1.0V IN0A AT +1V +1.0V V OUT 100 90 +1.8V SEL A/B +1.0V IN0A AT +0.5V +1.0V V OUT 10 0% IN0B AT -1V 0V -1.0V 10 0% IN0B AT -0.5V 0V -1.0V 10ns 10ns Figure 28. AD8183 Channel-to-Channel Switching Time Figure 31. AD8185 Channel-to-Channel Switching Time 100 90 SEL A/B +1.8V +1.0V 100 90 SEL A/B +1.8V +1.0V +0.05V 0V 10 0% +0.05V 0V 10 0% -0.05V -0.05V 10ns 10ns Figure 29. AD8183 Channel-to-Channel Switching Transient (Glitch) Figure 32. AD8185 Channel-to-Channel Switching Transient (Glitch) -8- REV. 0 AD8183/AD8185 VO = 200mV STEP 0.10V R = 1k L VO = 200mV STEP 0.1V R = 150 L 0.05V 0.05V 0.0V 0.0V -0.05V -0.05V -0.10V -0.1V 25mV 2ns 25mV 2ns Figure 33. AD8183 Small Signal Pulse Response; RL = 1 k Figure 36. AD8185 Small Signal Pulse Response; RL = 150 VO = 0.7V STEP 0.7V R = 1k L 0.6V 0.5V 0.4V 0.3V 0.2V 0.1V 0.0V VO = 1.4V STEP 1.4V R = 150 L 1.2V 1.0V 0.8V 0.6V 0.4V 0.2V 0.0V 100mV 2ns 200mV 2ns Figure 34. AD8183 Video Amplitude Pulse Response; RL = 1 k Figure 37. AD8185 Video Amplitude Pulse Response; RL = 150 VO = 2V STEP 1.0V R = 1k L VO = 2V STEP 1.0V R = 150 L 0.5V 0.5V 0.0V 0.0V -0.5V -0.5V -1.0V -1.0V 250mV 2ns 250mV 2ns Figure 35. AD8183 Large Signal Pulse Response; RL = 1 k Figure 38. AD8185 Large Signal Pulse Response; RL = 150 REV. 0 -9- AD8183/AD8185 THEORY OF OPERATION VIN RS CL VOUT 1k The AD8183 (G = +1) and AD8185 (G = +2) are triple-output, 2:1 multiplexers with TTL-compatible global input switching and output enable control. Optimized for selecting between two RGB (red, green, blue) video sources, the devices have high peak slew rates, maintaining their bandwidth for large signals. Additionally, the multiplexers are compensated for high phase margin, minimizing overshoot for good pixel resolution. The multiplexers also have video specifications that are suitable for switching NTSC or PAL composite signals. The multiplexers are organized as three independent channels, each with two input transconductance stages and one output transimpedance stage. The appropriate input transconductance stages are selected via one logic pin (SELECT A/B), such that all three outputs switch input connections simultaneously. The unused input stages are disabled with a "t-switch" scheme to provide excellent crosstalk isolation between "on" and "off" inputs. No additional input buffering is necessary, resulting in low input capacitance and high input impedance without additional signal degradation. The transconductance stages, NPN differential pairs, source signal current into the folded cascode output stages. Each output stage contains a compensating network and emitter follower output buffer. Internal voltage feedback sets the gain with the AD8183 being configured as a unity gain follower, and the AD8185 as a gain-of-two amplifier with a feedback network. This architecture provides drive for a reverse-terminated video load (150 ) with low differential gain and phase error for relatively low power consumption. Careful chip design and layout allow excellent crosstalk isolation between channels. One logic pin OE controls whether the three outputs are enabled, or disabled to a high-impedance state. The high impedance disable allows larger matrices to be built when busing the outputs together. Also, when not in use the outputs can be disabled to reduce power consumption. In the case of the AD8185 (G = +2), a feedback isolation scheme is used so that the impedance of the gain-of-two feedback network does not load the output. Note that full power bandwidth for an undistorted sinusoidal signal is often calculated using peak slew rate from the equation: Full Power Bandwidth = Peak Slew Rate (2 x x Sinusoid Amplitude) RS = 0 , CL = 5pF 75 0.5V RS = 15 , CL = 20pF 0.0V RS = 20 , CL = 20pF -0.5V 250mV 5ns Figure 39. Pulse Responses Driving Capacitive Loads Power Supply and Layout Considerations The AD8183 and AD8185 are very high performance muxes that require attention to several important design details to realize their specified performance. Good high-frequency layout rules must be carefully observed. A good design will start with a solid ground plane. All the GND pins of the part(s) should be directly connected to it. In addition, bypass capacitors should be connected from each supply pin (VCC and VEE) to the ground plane. It is suggested to use 0.01 F surface-mount chip capacitors as close to the IC as possible to provide high-frequency bypassing. For lower frequency bypassing, higher value tantalum capacitors-- at least 10 F--should be provided from both VCC and VEE to ground. These do not have to be as close to the IC pins, because parasitic inductance is not as big a factor at low frequencies. Please refer to AD8183/AD8185 Evaluation Board Operation Guide for further information. Crosstalk In normal operation the AD8183 and AD8185 will have signals at some of the input pins that are not switched to appear at the output. In addition, several signal paths will in general be active at one time. In any system that has high-frequency signals that are brought together in close proximity, there will be inevitable crosstalk, whereby some fraction of the undesired signals will appear at the outputs. This can result, for example, in ghost images in an RGB monitor muxing application. The AD8183 and AD8185 are capable of excellent lowcrosstalk performance. However, in order to realize the best possible crosstalk performance, certain design details should be followed. Most of the low-crosstalk specification is inherent in the part and will result from observing the power supply and layout consideration discussed above. This is because each of the input and output pins are separated by at least either a supply pin or a ground pin. This package architecture helps the crosstalk performance in at least three ways. First, the supply and ground pins provide extra physical separation between the input- and output-signal pins. Physical separation is a very effective technique for reducing crosstalk. Second, the supply and ground pins are at ac ground, and therefore provide a degree of shielding between the signals. This works for both capacitive crosstalk, which is due to voltages on the signals, and inductive crosstalk, which is due to currents that flow through the signal paths. Peak slew rate is not the same as average slew rate (25% to 75%) as typically specified. For a natural response, peak slew rate may be 2.7 times larger than average slew rate. Therefore, calculating a full power bandwidth with a specified average slew rate will give a pessimistic result. APPLICATIONS Driving Capacitive Loads When driving a large capacitive load, most amplifiers will exhibit peaking/ringing in pulse response. To minimize peaking, and to ensure stability for larger values of capacitive loads, a small resistor, RS, can be added between the output and the load capacitor, CL. This is shown in Figure 39. -10- REV. 0 AD8183/AD8185 Third, the additional power and ground pins also yield lower impedance on the power and ground lines, and therefore minimize the effects of shared impedances on crosstalk. Signal routing is also important for keeping crosstalk low. Shielding and separation should be used for signals that must run parallel over some length on the PC board. If signals must cross, the trace widths should be kept narrow, and the signals should cross at right angles to minimize the capacitance between the traces. 4:1 RGB Multiplexer A delay circuit is provided for each device to ensure that the outputs of one device are disabled before the outputs of the other are enabled. If the RGB signals contain the sync information, such as a syncon-Green, this circuit is all that is necessary for the full 4:1 RGB mux. However, if sync is carried on separate signals, such as in PCs, the sync signals can be multiplexed through a digital multiplexer that operates from the same SEL signals. The RC in the OE circuit is to ensure "Break-Before-Make" operation. Using the values shown, a 20 ns time constant is created. This will delay the enabling of the outputs of the new selection until after the other devices' outputs are disabled. This time can be shortened or eliminated if the system can tolerate the glitches caused by simultaneously enabled outputs. For selecting among four RGB sources to drive a monitor, two AD8185s can be combined to make a 4:1 RGB multiplexer. A circuit for this is shown in Figure 40. Each RGB source is connected to either the three "A" or "B" inputs of one of the AD8185s. In addition, all R signals are tied to "0" inputs, all G signals are tied to "1" inputs, and all B signals are tied to "2" inputs. All of these input signals should be terminated with the standard 75 to ground very close to the IC pins. Each of the outputs of the AD8185 has a series 75 resistor to provide a back termination for the monitor load. Whichever device is selected will drive the output signal through its three termination resistors. When terminated by the monitor, the voltage of these signals will be attenuated by a factor of two. This is normalized by the gain-of-two of the AD8185. Unlike many gain-of-two circuits, the impedance of the AD8185 is very high when it is disabled. This is due to a proprietary circuit that disconnects the feedback network from a low impedance when the part is disabled. R G B SOURCE 0 75 IN1A IN1B 75 R G B SOURCE 1 75 75 IN2A IN2B SEL A/B OE 200 100pF IN0A IN0B 75 OE OE 75 OUT2 BLUE OE 75 OUT1 GREEN TO MONITOR 75 75 IN0A IN0B OE 75 OUT0 RED EVALUATION BOARD POWER AND GROUND There are three power supply pins on the board. "VCC" is +5 V analog, "V EE" is -5 V analog, and "DVCC" is +5 V digital. These three power supply pins should be connected to good quality, low noise supplies. If the same 5 V power supply is used for both analog and digital, separate cables should be run from the power supply to the evaluation board's analog and digital power supply pins. Three 10 F tantalum capacitors (C1-C3) are located under the power connector to decouple the power supplies as they first enter the board. As the three supplies get close to the part, they are again decoupled with 0.1 F ceramic capacitors (C4-C6). Finally, each power pin of the device is locally decoupled with a 0.01 F ceramic capacitor (C7-C15). The board has a separate analog and digital ground plane. With the jumper at W5 installed, these two ground planes are tied together on the board. Generally, this jumper should remain installed. INPUTS AND OUTPUTS R G B SOURCE 2 75 75 OUT0 The evaluation board has been carefully laid out to demonstrate the high speed performance of the device. Optimized for video applications, all signal inputs are terminated with 75 resistors to ground (R1-R6). The three outputs are backterminated with 75 series resistors (R12-R14). Stripline techniques are used to achieve a 75 characteristic impedance on the input and output lines. See Figure 41 for the arrangement of the PCB layers. 0.005" (127mm) TOP LAYER 0.0176" (447mm) 75 IN1A IN1B 75 OE 75 OUT1 R G B SOURCE 3 SEL 0 SEL 1 200 100pF 75 75 IN2A IN2B SEL A/B OE OE 75 OUT2 0.028" (711mm) 0.0026" (66mm) 75 SIGNAL LAYER POWER LAYER 0.005" (127mm) 50 SIGNAL LAYER 0.0038" (96.5mm) Figure 41. PCB Dimensions Figure 40. 4:1 RGB Multiplexer Two control bits are required to select the input source for the RGB signals. One is applied to each of the SEL A/B inputs of each device to select between the two input sources for that device. The other bit controls the OE inputs of the two devices. REV. 0 In addition, 75 BNC connectors are used on the six inputs (J1-J6) and three outputs (J7-J9). The connectors are arranged in a crescent around the device. This results in all the input and output signal traces having the same length. Unused regions of the multilayer board are filled up with ground planes. As a -11- AD8183/AD8185 result, the input and output traces, in addition to having a controlled impedance, are well shielded. SEL A/B AND OE 41 for the arrangement of the PCB layers. If J10 is used, the user may wish to install a 50 termination resistor at R10. OE (Pin 23 of the device) allows the three outputs to be enabled or disabled. When OE is at logic low, (equal to or less than 0.8 V), Outputs 0, 1, and 2 are enabled. When OE is at logic high, (equal to or greater than 2.0 V), Outputs 0, 1, and 2 are disabled (placed into a high impedance state). Once again, there are two different ways to provide OE to the device: using a jumper or a BNC connection. With the jumper in the W2 position, OE is tied to ground. This enables the outputs. With the jumper in the W1 position, OE is tied to 5 V, through pull-up resistor R16. This selects "Hi Z," or high impedance, and the outputs are disabled. If faster use of OE is desired, the 50 BNC connector at J11 can be used. If J11 is used, there must NOT be a jumper on W1 and W2. Microstrip line techniques provide a 50 characteristic impedance from J11 to the device. Please refer to Figure 41 for the arrangement of the PCB layers. If J11 is used, the user may wish to install a 50 termination resistor at R11. DVCC SEL A/B (Pin 22 of the device) allows the A or B inputs to be selected. When SEL A/B is at logic low, (equal to or less than 0.8 V), inputs 0A, 1A and 2A are directed to OUTPUTs 0, 1, and 2, respectively. When SEL A/B is at logic high, (equal to or greater than 2.0 V), inputs 0B, 1B, and 2B are directed to OUTPUTs 0, 1, and 2, respectively. There are two ways to provide SEL A/B to the device: using a jumper or a BNC connection. With the jumper in the W4 position, SEL A/B is tied to ground. This selects the A inputs. With the jumper in the W3 position, SEL A/B is tied to 5 V, through pull up resistor R15. This selects the B inputs. If faster use of SEL A/B is desired, the 50 BNC connector at J10 can be used. If J10 is used, there must NOT be a jumper on W3 and W4. Microstrip line techniques provide a 50 characteristic impedance from J10 to the device. Please refer to Figure DVCC P1 1 DVCC + C3 10 F C6 0.1 F DGND DGND DGND DGND P1 2 VEE DGND VEE P1 4 + C2 10 F AGND AGND C5 0.1 F AGND VEE AGND P1 5 VCC AGND VCC R16 20k W1 OE W2 VCC P1 6 + C1 10 F C4 0.1 F AGND VCC VCC R15 20k W3 W4 SEL A/B AGND DGND OE J11 50 MICROSTRIP LINE R11 50 OPTIONAL DGND VCC C15 0.01 F 50 MICROSTRIP LINE R10 50 OPTIONAL DGND VCC C14 0.01 F AGND R14 75 VEE C13 0.01 F AGND R13 75 VCC C12 0.01 F AGND R12 75 VEE DVCC VCC 75 75 75 DGND J10 SEL A/B IN0A J1 75 R1 75 AGND STRIPLINE IN1A J2 75 R2 75 AGND STRIPLINE DUT 1 AGND STRIPLINE IN2A J3 75 R3 75 AGND STRIPLINE VCC VEE C7 0.01 F AGND C8 0.01 F AGND DGND 2 3 AGND 4 5 6 7 8 9 10 IN2B J4 75 R4 75 AGND STRIPLINE AGND IN1B J5 75 R5 75 AGND STRIPLINE AGND 11 12 VCC 24 IN0A 23 OE DGND 22 IN1A SEL A/B 21 AGND VCC 20 IN2A OUT0 19 VCC AD8183/ VEE 18 VEE AD8185 OUT1 VCC 17 IN2B OUT2 16 AGND 15 VEE IN1B 14 DVCC AGND VCC 13 IN0B C9 0.01 F W5 AGND C10 0.01 F DGND J9 OUT0 STRIPLINE J8 OUT1 STRIPLINE J7 OUT2 C11 0.01 F AGND IN0B J6 75 R6 75 AGND STRIPLINE AGND DGND Figure 42. Evaluation Board Schematic -12- REV. 0 AD8183/AD8185 Figure 43. Component Side Silkscreen Figure 44. Board Layout (Component Side) REV. 0 -13- AD8183/AD8185 Figure 45. Board Layout (75 Signal Layer) Figure 46. Board Layout (Ground Plane) -14- REV. 0 AD8183/AD8185 Figure 47. Board Layout (Circuit Side;) 50 Signal Layer Figure 48. Circuit Side Silkscreen REV. 0 -15- AD8183/AD8185 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-Lead Plastic TSSOP (RU-24) C3689-5-10/99 0.028 (0.70) 0.020 (0.50) 0.311 (7.90) 0.303 (7.70) 24 13 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 1 12 PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX SEATING PLANE 0.0256 (0.65) 0.0118 (0.30) BSC 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090) 8 0 -16- REV. 0 PRINTED IN U.S.A. |
Price & Availability of AD8183
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